1. Field of Invention
The present invention relates to a fabrication method for an active element array substrate, and more particularly, to a fabrication method for a thin film transistor array substrate.
2. Description of Related Art
The demands and researches on display apparatus are increasing. The CRT (cathode ray tube) display is a mainstream in the display apparatus due to its great display quality. However, the tendency on the display apparatus directs to light, compact, low power consumption and low radiation but the CRT displays do not meet the requirements. Therefore, the TFT-LCD (Thin Film Transistor Liquid Crystal Display) displays play an important role now.
A TFT-LCD display is formed by a LCD panel and a backlight module. The LCD panel is formed by a TFT array substrate, a color filter substrate and liquid crystal layers sandwiched therebetween. The backlight module provides light sources for the LCD panel for display.
FIGS. 1A˜4A show top views of a conventional TFT array substrate and FIGS. 1B˜4B show cross-sectional views taken along the line I-I′ in FIGS. 1A˜4A.
Please refer to FIGS. 1A and 1B. A first metal layer having a thickness with several thousand angstroms is formed on a substrate 110 by sputtering process. A first mask process is performed on the first metal layer for forming scan lines 122, scan pads 124, common lines 132 and common pads 134. One end of each of the scan lines 122 is electrically connected to one of the scan pads 124 and one end of each of the common lines 132 is electrically connected to one of the common pads 134.
Please refer to FIGS. 2A and 2B. A dielectric layer, a semiconductor layer and an ohmic contact layer are sequentially formed over the substrate 110. The dielectric layer, the semiconductor layer and the ohmic contact layer are made of SiNx, a-Si (amorphous silicon) and n+-Si, respectively. A contact metal layer is formed over the ohmic contact layer by sputtering. A second mask process is performed on the resulting structure for sequentially forming a patterned dielectric layer 142, a patterned semiconductor layer 144, a patterned ohmic contact layer 146 and a patterned contact metal layer 148. For improving the yield, the patterned dielectric layer 142, the patterned semiconductor layer 144, the patterned ohmic contact layer 146 and the patterned contact metal layer 148 cover the common lines 132 and portions of the scan lines 122. In other words, the resulting structure is completed-etched or over-etched for removing the patterned dielectric layer 142, the patterned semiconductor layer 144, the patterned ohmic contact layer 146 and the patterned contact metal layer 148 in other regions. So, the exposed common pads 134, the scan pads 124 and the portions of the scan lines may be slighted damaged (etched), for example those in regions A1 and B1 of FIG. 2B. Wirings in the region A1 are exposed and portions of the scan lines are exposed in the region B1.
Please refer to FIGS. 3A and 3B. A transparent conductive layer and a second metal layer are sequentially disposed over the substrate 110. Then, a third mask process is performed for forming a patterned transparent conductive layer 152 and a patterned second metal layer 154. The patterned transparent conductive layer 152 and the patterned second metal layer 154 are defined to form data lines 162, data pads 164, source/drain electrodes 172 and pixel electrodes 174. One of each of the data lines 162 is electrically connected to one of the data pads 164. In channel etching, because portions of scan lines 122 are exposed (for example, in the region A1 and B1), the portions of the scan lines 122 have a reduced thickness and accordingly the resistance thereof is higher or they may be broken. The yield is negatively affected.
Please refer to FIGS. 4A and 4B. A passivation layer 182 is formed over the substrate 110. The passivation layer 182 is made of SiNx. A fourth mask process is performed for forming first openings 124a, second openings 164a and third openings 134a. The patterned transparent conductive layer 152 over the scan pad 124 is exposed by the first opening 124a. The patterned transparent conductive layer 152 over the data pads 164 is exposed by the second openings 164a. The patterned transparent conductive layer 152 over the common pads 134 is exposed by the third openings 134a. The patterned second metal layer 154 of the pixel electrodes 174 is totally removed for exposing the patterned transparent conductive layer 152 of the pixel electrodes 174. By the above, the conventional TFT array substrate is almost made.
Because of the four-round mask processes and for improving the yield, the patterned dielectric layer 142, the patterned semiconductor layer 144, the patterned ohmic contact layer 146 and the patterned contact metal layer 148 outside predetermined regions have to be totally removed. The exposed common pads 134 and the portions of the scan lines 122 (for example, in the regions A1 and B1 of FIGS. 2A and 2B) may be slightly damaged. Besides, in the third mask process, the exposed scan lines 122 may be further damaged to reduce thickness thereof and may be broken. (for example, in the regions A1 and B1 of FIGS. 3A and 3B).
The distances between the pixel electrodes 174 and the data lines 164 are kept for preventing short therebetween. This reduces the aperture ratio.